Freescale Semiconductor /MKL28T7_CORE1 /LPIT0 /SETTEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SETTEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SET_T_EN_0 0 (0)SET_T_EN_1 0 (0)SET_T_EN_2 0 (0)SET_T_EN_3

SET_T_EN_0=0, SET_T_EN_1=0, SET_T_EN_3=0, SET_T_EN_2=0

Description

Set Timer Enable Register

Fields

SET_T_EN_0

Set Timer 0 Enable

0 (0): No effect

1 (1): Enables the Timer Channel 0

SET_T_EN_1

Set Timer 1 Enable

0 (0): No Effect

1 (1): Enables the Timer Channel 1

SET_T_EN_2

Set Timer 2 Enable

0 (0): No Effect

1 (1): Enables the Timer Channel 2

SET_T_EN_3

Set Timer 3 Enable

0 (0): No effect

1 (1): Enables the Timer Channel 3

Links

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